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INTEGRATED CIRCUITS
DATA SHEET
PCA1070 Multistandard programmable analog CMOS transmission IC
Product specification Supersedes data of 1996 Mar 06 File under Integrated Circuits, IC03 1997 Jun 20
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
FEATURES * Line interface with: - Voltage regulator with programmable DC voltage drop - Programmable set impedance - Output to control an external switching MOS transistor for pulse dialling - Programmable DC voltage during pulse dialling - Circuitry for short DC settling time * Interface to peripheral circuits with: - Supply for microcontroller and DTMF diallers - Input to sense supply voltage of microcontroller and output for reset of microcontroller - I2C-bus (programming of parameters, control of all logic signals) - High impedance DTMF signal input - Input for external oscillator signal with on-chip DC blocking - Power-down via the I2C-bus - Stabilized supply for electret microphone * Microphone and DTMF amplifiers: - Low-noise microphone preamplifier suitable for various types of microphones - Symmetrical high impedance microphone preamplifier inputs - Programmable gain for microphone and DTMF channels - Sending mute via the I2C-bus to disable microphone amplifier and enable DTMF amplifier - Sending mute also to be used as privacy switch - Dynamic limiting (speech controlled) to prevent distortion of line signal and sidetone; programmable maximum sending level * Receiving amplifier: - Suitable for various types of earpieces (including piezo) - Programmable gain and hearing protection level - Receiving mute via the I2C-bus to disable receiving amplifier and enable DTMF confidence tone - On-chip anti-sidetone circuit with programmable sidetone balance - Confidence tone in the earpiece during DTMF dialling
PCA1070
* Facility to regulate parameters with line current: - Value of DC line current (bit code) readable via the I2C-bus - Line loss compensation with fully software programmable characteristics (control range, stop current) of microphone/earpiece/DTMF amplifiers - Fully software programmable control of sidetone balance and DC voltage drop as a function of line length. APPLICATIONS * Wired telephony (basic till feature phones) * Combi-terminals (e.g. telephone and answering machine or FAX) * Modems and base units of cordless telephones. GENERAL DESCRIPTION The PCA1070 is a CMOS integrated circuit performing all speech and line interface functions in fully electronic telephone sets. The device requires a minimum of external components. The transmission parameters are programmable via the I2C-bus. This makes the IC adaptable to nearly all worldwide country requirements and to a various range of speech transducers, without changing the (few) external components. The parameters are stored in the EEPROM of a microcontroller and are loaded into the PCA1070 during the start-up phase of the transmission IC after hook-off. The PCA1070 also allows adaptation to the connected telephone line by reading the line current via the I2C-bus and processing it in the microcontroller.
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCA1070P PCA1070T BLOCK DIAGRAM DIP24 SO24 DESCRIPTION plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm
PCA1070
VERSION SOT101-1 SOT137-1
handbook, full pagewidth
positive line peripheral supply
SLPE LN 24 TX 1 5
REG 2
LSI 4
DOC 3
V DD 23
VMC 22
RMC 18
OREC(1) 8
Vref 7 14 QR
LINE INTERFACE SCR 6
POWER CONTROL
BIAS AND REFERENCE
BTL RECEIVE OUTPUT
15 QR
VSS 13
VSLPE Zset DST ANTI SIDETONE
PRES
PD DPI RRG
maximum level load select (0 dB) RECEIVE PROG-AMP (-6 dB)(2)
PCA1070
sidetone balance Iline SEND PROG-AMP (15 dB)(2)
(-25 dB)
receive mute
gain Gra 17 DTMF 10 V P
GAIN CONTROL gain Gma line current DYNAMIC LIMITER (0 dB)
MICROPHONE SUPPLY
12 MIC MICROPHONE PREAMPLIFIER (20 dB)
(0 dB)
11 MIC
CLOCK INTERFACE 19 CLK
I C-BUS INTERFACE 21 SDA 20 SCL
2
TEST CONTROL 16 TST(1)
send mute threshold 9 OMIC(1)
MLA944
(1) Test pins. (2) Default value.
Fig.1 Block diagram.
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
PINNING SYMBOL TX REG DOC LSI LN SCR Vref OREC OMIC VP MIC- MIC+ VSS QR+ QR- TST DTMF RMC CLK SCL SDA VMC VDD SLPE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION drive output voltage regulator decoupling dial output connection line signal input positive line terminal sending current resistor voltage reference decoupling output receiving preamplifier; to be left open-circuit in application output microphone preamplifier; to be left open-circuit in application supply for electret microphones inverting input microphone preamplifier non-inverting input microphone preamplifier negative line terminal non-inverting output of receiving amplifier inverting output of receiving amplifier test pin; to be connected to VSS in application dual tone multi-frequency input reset output for microcontroller clock signal input serial clock line input; I2C-bus serial data line input/output; I2C-bus input to sense supply voltage microcontroller positive supply decoupling slope (DC resistance) adjustment
handbook, halfpage
PCA1070
TX REG DOC LSI LN SCR Vref OREC OMIC
1 2 3 4 5 6
24 SLPE 23 VDD 22 VMC 21 SDA 20 SCL 19 CLK
PCA1070
7 8 9 18 RMC 17 DTMF 16 TST 15 14 13
MGE338
VP 10 MIC- 11 MIC+ 12
QR- QR+ VSS
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
FUNCTIONAL DESCRIPTION All values in the Chapter "Functional description" are typical unless stated otherwise.
handbook, halfpage
PCA1070
LN CP CREG CLSI Ca Ra Zset
Line interface DC VOLTAGE DROP Power for the PCA1070 and its peripheral circuits is obtained from the telephone line. The IC develops its own supply voltage at VDD and regulates its DC voltage drop between pins SLPE and VSS. This voltage (VSLPE) can be programmed via the I2C-bus interface between 3.1 to 5.9 V and is default at 4.7 V (see Table 8). The DC line voltage at pin LN can be calculated using the following equation: VLN = VSLPE + (Iline - ILN) x RLN-SLPE where: ILN = DC bias current flowing into pin LN (3 mA if Iline > 17 mA) RLN-SLPE = external 20 resistor between LN and SLPE. At line currents below 6 mA the DC voltage VSLPE is automatically adjusted to a lower value. This means that the operation of more sets, connected in parallel, is possible with reduced sending and receiving levels and relaxed performance. At line currents below 16 mA the DC bias current ILN is reduced from 3 mA to a lower value to ensure maximum possible transmit level capability under all line current conditions. SET IMPEDANCE In normal conditions Iline >> ILN and the static behaviour is equivalent to a voltage regulator diode with a series resistor RLN-SLPE. In the audio frequency range the dynamic impedance ZLN is determined mainly by the internal component Zset = Ra + (Rb // C). The equivalent impedance ZLN is shown in Fig.3. The values of Ra, Rb and C can be programmed via the I2C-bus interface (see Tables 9, 10 and 11).
RLN-SLPE
SLPE Leq VSLPE
REG
LSI Rb C
RP
RLSI
MGE342
VSS
Fig.3 Equivalent impedance ZLN.
where: Ca = DC blocking capacitor (influence negligible at f 300 Hz for given value of CLSI) CLSI = capacitor at pin LSI (100 nF) CP = internal capacitor (12 nF) CREG = capacitor at pin REG (470 nF) Leq = artificial inductor (= RP x RLN-SLPE x CREG = 10.1 H at VSLPE = 4.7 V) RLN-SLPE = DC slope resistance (20 ) RP = internal resistor (1075 k at VSLPE = 4.7 V) RLSI = internal resistor (240 k). SUPPLY FOR PERIPHERAL CIRCUITS The supply voltage VDD can be used for peripheral circuitry. The supply capabilities depend on the programmed DC voltage drop VSLPE and on several other parameters as given in the following equation: VDD = VSLPE - (IDD + Ip + IVP) x RSLPE-VDD where: IDD = internal current consumption PCA1070 (2.3 mA) Ip = current to peripheral circuitry IVP = current taken from VP for electret microphone RSLPE-VDD = external resistor between SLPE and VDD.
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5
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
DC STARTING AND SETTLING TIME The IC is equipped with circuitry for fast DC start-up. This circuit is automatically activated as soon as VDD reaches 3 V after hook-off, and is deactivated when VSLPE drops below 5.9 V. This ensures that only a relatively short time is needed to reach the default DC setting (VSLPE) of the circuit and that VDD will not exceed the maximum permitted voltage of 6 V. The start-up circuit can also be activated under software control by setting bit code DST to logic 1 via the I2C-bus. The start-up time can be optimized by programming the bit code DST to logic 1 during the start-up procedure. In practice this is possible as soon as the microcontroller has become operational. The DST bit can also be used to quickly restore the DC settings (VSLPE) after long line breaks or during reprogramming of VSLPE. It should be noted that the AC impedance into pin LN is reduced considerably when DST = 1. Power control POWER-DOWN/STANDBY MODES INTERNAL RESET PCA1070 The PCA1070 has an internal reset circuit that monitors the supply voltage VDD. If VDD is below the threshold level (1.2 V) then the circuit is in reset-mode. In this mode the current consumption is low and the internal reset is active and writes the default values into all registers. The status bit PRES will be set to logic 1. The microcontroller can read this bit via the I2C-bus interface; once read it will be set to logic 0 again. When VDD passes the threshold (increasing VDD), the circuit becomes partly active and the internal ring/speech detector will be activated (see Section "Start-up and switch-off behaviour"). RESET OUTPUT FOR MICROCONTROLLER The voltage at pin VMC (microcontroller supply voltage) is monitored by a reset circuit. If VVMC is below the threshold level the output RMC is set to logic 1. This threshold level is 2 V in the normal operating and power-down mode and 2.1 V in the standby mode (see Fig.4).
PCA1070
handbook, halfpage
MGE339
VVMC
low voltage condition VRESET
0 RMC logic 1
logic 0
Fig.4 VMC timing diagram.
The circuit can be set in power-down or standby mode. These modes are intended for use with pulse dialling during long line breaks and applications with memory retention. With control bits PDx = 01, the circuit is in the power-down mode; the typical current consumption at pin VDD is reduced from IDD = 2.3 mA to 30 A; the typical current consumption at pin VMC is 4 A. When PDx = 11 the circuit is in the standby mode and IDD and IVMC are reduced to 2 A. In both conditions (power-down and standby) the voltage stabilizer will be disabled. START-UP AND SWITCH-OFF BEHAVIOUR This description refers to the basic application where VDD and VMC are connected together and one supply capacitor is used (see Fig.8).
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
Speech condition
After hook-off, line current will be applied to the line input LN and the supply capacitor connected to VDD and VMC will be charged. The internal reset signal will change from logic 1 to logic 0 when VDD passes the threshold level (1.2 V) and the circuit becomes partly active [the line interface part is kept in power-down mode, so that all of the line current is available to charge the supply capacitor(s)]; The PCA1070 can receive data via the I2C-bus (standard I2C specifications are fulfilled for VDD 2.5 V; relaxed performance for VDD = 1.8 to 2.5 V). When VVMC passes the microcontroller reset level of 2 V (2.1 V in standby mode) the output RMC changes from logic 1 to logic 0 and the circuit is switched to the normal operating mode. After hook-on VVMC decreases and the output RMC will change from logic 0 to logic 1 when VVMC passes the threshold level, however the PCA1070 will stay in the normal operating mode until the internal reset at 1.2 V takes place. By decreasing VDD the internal reset signal will change from logic 0 to logic 1 when VDD passes 1.2 V and the circuit will go into the reset mode (line interface part in power-down and all programmable parameters reset to default values). DIAL PULSE INPUT (DPI)
PCA1070
The DPI bit controls output DOC (open-drain) that drives the gate of an external MOS interrupter transistor. DPI is controlled via the I2C-bus interface. If DPI is set to logic 1, pin DOC will be pulled down to switch-off the MOSFET to generate a line break. If DPI = 0 pin DOC is high-ohmic and the interrupter transistor will conduct the line current. Sending channel The PCA1070 has symmetrical microphone inputs and accepts input signals of maximum 70 mV (peak) for THD = 2% (VDD 2.5 V). Its input impedance is 100 k and its gain is default 41 dB. Dynamic, magnetic, piezoelectric and electret (with built-in FET source follower) microphones can be used. Some possible microphone arrangements are shown in Fig.5. The gain of the sending channel can be programmed between 30 dB and 51 dB in 1 dB steps using bit code GMAx (6 bits). The gain of the microphone preamplifier is 20 dB (with dynamic limiter not active) and GMAx sets the gain of the `sending prog-amp' (allowed range Gma = 4 to 25 dB). The gain of the line interface is 6 dB. Thus the total gain of the sending channel (GM) is as follows: GM = 20 + Gma + 6 (dB) Default: GM = 20 + 15 + 6 = 41 dB Where Gma = `gain sending prog-amp'. Programming the gain of the `sending prog-amp' is given in Table 13.
Ringer condition
In this condition the supply capacitor connected to VDD and VMC is charged by the rectified ringer signal; no line current is applied to pin LN. VDD and VVMC are increasing and when VDD passes the internal reset threshold level (1.2 V), the internal ring/speech-detector will be activated and the circuit will switch to the standby condition (IDD < 5 A; IVMC < 5 A) before the voltage at VMC reaches the threshold level for microcontroller reset. When VVMC passes this threshold level (2.1 V) output RMC changes from logic 1 to logic 0 and the circuit will stay in the standby mode until line current is applied to pin LN. By setting the `Reset Ring' control bit (RRG) to logic 1 via the I2C-bus interface, the ring/speech detector will be disabled.
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
PCA1070
handbook, full pagewidth
VP
VP
VP
MIC+
MIC+
MIC+
MIC+
MIC-
MIC-
MIC-
MIC-
VSS
VSS
VSS
(a)
(b)
(c)
(d)
MGE341
(a) Dynamic or piezo. (b) Low impedance electret with built-in pre-amplifier. (c) High impedance electret with built-in pre-amplifier. (d) Symmetrical connection of electret.
Fig.5 Microphone arrangements.
Dynamic limiter To prevent distortion of the transmitted speech signal, the gain of the microphone amplifier is reduced rapidly when signal peaks on the line exceed an internally determined threshold level. The time in which the gain is reduced, the attack time, is very short. The circuit stays in this gain-reduced condition until the peaks of the sending signal remain below the threshold level. The sending gain then returns to normal after a time also determined on the chip, the release time. The threshold level of the AC peak-to-peak line voltage on pin LN is default at 3.5 V (p-p). A level of 2.6 V (p-p) can be programmed by setting bit code DLT to logic 1. The internal threshold level is lowered automatically if the DC voltage setting of the circuit (VSLPE) is not high enough to reach the programmed level. Also when the DC current in the transmit output stage is insufficient to drive the line load, the internal threshold level is lowered automatically. Dynamic limiting considerably improves sidetone performance in over-drive conditions (less distortion and limited sidetone level).
DTMF channel The PCA1070 has an asymmetrical DTMF input. Its input impedance is 200 k // 45 pF and its gain is default at 21 dB. DTMF signals can be sent to the line by setting control bit `Sending Mute' (SM) to logic 1 (default SM = 0); by setting `Receiving Mute' (RM) also to logic 1 (default RM = 0), the dialling tones are also sent to the receiving output to generate a confidence tone in the earpiece. The gain between the DTMF input and the line LN can be programmed between 1 dB and 21 dB in 1 dB steps using bit code GMAx (6 bits). The confidence tone gain (between DTMF input and earpiece outputs QR) can be programmed between -40 dB and -19 dB (symmetrical drive of earpiece) using bit code GRAx (6 bits). GMAx sets the gain of the `sending prog-amp' (recommended range in DTMF mode for Gma = -5 to 15 dB) and GRAx sets the gain of the `rec prog-amp' (allowed range Gra = -25 to 0 dB).
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
The total gain of the DTMF channel between the DTMF input and the line LN is as follows: GDTMF = Gma + 6 (dB) Default GDTMF = 15 + 6 = 21 dB The confidence tone gain (DTMF to QR outputs) is: With symmetrical drive of earpiece GCTs = Gra - 19 (dB) Default GCTss = -6 - 19 = -25 dB. At low gain settings (Gra < -10 dB), the confidence tone gain will be slightly higher than the calculated value. This is caused by a residual signal. Programming the gain of the `sending prog-amp' and the `rec prog-amp' is given in Table 13. Receiving channel The gain of the receiving channel is defined between the line connection LN and the earpiece outputs QR+ and QR-. Its voltage gain is default -6 dB (differential drive). The LN terminal accepts receiving signals up to 1 V (RMS) for THD = 2%. The outputs may be used to connect dynamic, magnetic or piezoelectric earpieces with single-ended or differential drive. The load select bit RFC is set default to logic 1 to guarantee stable operation in case of a capacitive load (piezoelectric earpiece). With a resistive load (dynamic capsule) RFC should be set to logic 0 via the I2C-bus interface to obtain optimum performance with respect to distortion and bandwidth. Two levels for hearing protection can be selected via the I2C-bus interface with control bit HPL. The earpiece arrangements are illustrated in Fig.6.
PCA1070
The gain of the receiving channel can be programmed between -19 dB and +11 dB (symmetrical drive) in 1 dB steps using bit code GRAx (6 bits). GRAx sets the gain of the `rec prog-amp' (allowed range Gra = -19 dB to +11 dB; default Gra = -6 dB). The total gain of the receiving channel is as follows: Symmetrical drive GRS = Gra (dB) Default GRS = -6 dB. Asymmetrical or single-ended drive GRA = GRS - 6 (dB) Default Gra = -6 - 6 (dB) = -12 dB. Programming the gain Gra of the `rec prog-amp' is given in Table 13. Sidetone balance The PCA1070 has an on-chip anti-sidetone circuit. An internal balance impedance Zoss can be programmed via the I2C-bus interface to match the external line impedance Zline to give optimum sidetone suppression. Zoss = Rsa + (Rsb // Cs). Programming the sidetone balance impedance is given in Tables 14, 15 and 16. Line current control The DC line current can be read via the I2C-bus interface. This information can be used for the adaptation of transmission parameters (for example line loss compensation, sidetone balance and DC characteristic). The bit code LCx as a function of line current is given in Table 17.
handbook, halfpage
QR+
QR+
QR-
QR- VSS
MGE340
(a) symmetrical
(b) single-ended
Fig.6 Earpiece arrangements.
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
I2C-BUS PROGRAMMING Table 1 Programmable parameters The following parameters (see Fig.1) can be programmed by means of a bit code via the I2C-bus: SYMBOL VDCx ZSAx ZSBx ZSPx DST PDx DPI RRG HPL RFC ZOSAx ZOSBx ZOSPx RM GRAx GMAx SM DLT Table 2 receiving mute gain Gra gain Gma sending mute threshold Readable parameters DST PD DPI RRG maximum receiving level load select sidetone impedance PARAMETER VSLPE set impedance BLOCK line interface line interface line interface line interface line interface power control power control power control BTL receiving output BTL receiving output anti-sidetone anti-sidetone anti-sidetone receiving mute receiving prog-amp sending prog-amp sending mute dynamic limiter BITS 3 3 3 4 1 2 1 1 1 1 4 4 4 1 6 6 1 1
PCA1070
DESCRIPTION DC voltage SLPE-VSS Ra of set impedance Rb of set impedance fp (pole frequency) of set impedance DC Start Time Power-Down Dial Pulse Input Reset RinG detector Hearing Protection Level Resistive/Capacitive load Rsa of sidetone impedance Rsb of sidetone impedance Cs of sidetone impedance Receiving Mute Gain receiving prog-amp Gain sending prog-amp Sending Mute Dynamic Limiter Threshold
The following parameters (see also Fig.1) can be read as a bit code via the I2C-bus: SYMBOL PRES LCx I2C interface The I2C-bus interface (see "The I2C-bus and how to use it" 12NC: 9398 393 40011) is used to program the transmission parameters and control functions. Table 3 A6 0 Device address A5 1 A4 0 A3 0 A2 0 A1 1 A0 0 R/W X PARAMETER PRES line current BLOCK power control gain control BITS 1 5 Line Current DESCRIPTION PCA1070 Reset
All functions can be accessed by writing an 8-bit word to the PCA1070. In order to set up the PCA1070, a control message consisting of the device address, a R/W bit, a subaddress byte and one or more data bytes must be written to the PCA1070. If more than one data byte follows the subaddress, these bytes are stored in the successive registers by the automatic increment feature.
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
Table 4 The control word format for the slave receiver DEVICE ADDRESS S Note 1. This bit is R/W. Table 5 Bit arrangement of each data byte used in the control word: PCA1070 receive (see note 1) SUB ADDRESS H00 H01 H02 H03 Sending channel Receiving channel Control Note 1. The bits that are not indicated must be set to logic 0. Table 6 The control word format for the slave transmitter DEVICE ADDRESS S Note 1. Change in direction of R/W bit. Table 7 PCA1070 send FUNCTION PCA1070 status Notes D7 PRES(1) D6 - D5 - D4 LC4(2) D3 LC3(2) D2 LC2(2) 0 1 0 0 0 1 0 1(1) A D7 D6 DATA/STATUS BYTE D5 D4 D3 D2 D1 H04 H05 H06 DLT RFC PD1 HPL PD0 ZOSB3 ZOSP3 D7 D6 VDC2 ZOSB2 ZOSP2 ZSB2 D5 VDC1 ZOSB1 ZOSP1 ZSB1 GMA5 GRA5 D4 VDC0 ZOSB0 ZOSP0 ZSB0 GMA4 GRA4 RRG ZSP3 GMA3 GRA3 RM ZOSA3 ZOSA2 ZSA2 ZSP2 GMA2 GRA2 SM D3 D2 0 100010 0(1) SUB ADDRESS
PCA1070
DATA/CONTROL BYTE
A I7 I6 I5 I4 I3 I2 I1 I0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
FUNCTION DC voltage Sidetone and set impedance
D1
D0 DST
ZOSA1 ZSA1 ZSP1 GMA1 GRA1
ZOSA0 ZSA0 ZSP0 GMA0 GRA0 DPI
D0
A
P
D1 LC1(2)
D0 LC0(2)
1. Indicates if PCA1070 has received internal reset; PRES will be set to logic 1 with internal reset and is set to logic 0 after reading the register via the I2C-bus. 2. Information about value of line current.
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
WRITE AND READ TABLES DC voltages Table 8 DC voltage at pin SLPE VDC2 0 0 0 0 1 1 1 1 Set impedance Programming the impedance in the audio frequency range seen at pin LN: Ra + (Rb // C) Table 9 Programming Ra ZSA2 0 0 0 0 1 1 1 Notes ZSA1 0 0 1 1 0 0 1 ZSA0 0 1 0 1 0 1 X Ra () 0 100 200 300 400 500 600 VDC1 0 0 1 1 0 0 1 1 VDC0 0 1 0 1 0 1 0 1 VSLPE (V) 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9
PCA1070
REMARK
default
REMARK
default
note 1 notes 1 and 2
1. For Zset combinations where Ra = 0 only Rb = 600 is allowed. If Ra 500 it is obligatory that Rb = 0. This is to safeguard stable operation of the line interface under all practical conditions. If Zref requires Ra = 0 and Rb 600 use Ra = 100 instead and reduce the original Rb by 100 . 2. X = don't care.
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
Table 10 Programming Rb ZSB2 0 0 0 0 1 1 Notes ZSB1 0 0 1 1 X X ZSB0 0 1 0 1 0 1 Rb () 0 600 700 800 900 1000
PCA1070
REMARK note 1
default note 2 note 2
1. For Zset combinations where Ra = 0 only Rb = 600 is allowed. If Ra 500 it is obligatory that Rb = 0. This is to safeguard stable operation of the line interface under all practical conditions. If Zref requires Ra = 0 and Rb 600 use Ra = 100 instead and reduce the original Rb by 100 . 2. X = don't care. Table 11 Programming pole frequency: CORRESPONDING VALUE OF C (nF)(1) ZSP3 0 0 0 0 0 0 0 0 1 Notes 1. 1 C = -----------------------------2 x R b x f p ZSP2 0 0 0 0 1 1 1 1 X ZSP1 0 0 1 1 0 0 1 1 X ZSP0 0 1 0 1 0 1 0 1 X fp (Hz) 828 1095 1448 1915 2533 3350 4430 5859 12000 Rb (600 ) 320 242 183 139 105 79 60 45 22 Rb (700 ) 275 207 157 119 90 68 51 39 19 Rb (800 ) 240 182 137 104 79 59 45 34 17 Rb (900 ) 214 161 122 92 70 53 40 30 15 Rb (1000 ) 192 145 110 83 63 48 36 27 13 note 2 default REMARK
2. X = don't care. Reset functions Monitoring of internal reset PCA1070. Table 12 Status bit PRES PRES 1 0 DESCRIPTION internal reset has occurred; default values in all registers register has been read via the I2C-bus interface
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
Programmable amplifier (prog-amp)
PCA1070
An identical programmable amplifier called `prog-amp' is used both in the sending and receiving channel. The bit codes GMAx and GRAx are given in Table 13. The permitted adjustment range differs for the two amplifiers and is also different for DTMF and speech mode. This is indicated in the corresponding sections. Table 13 Bit code prog-amp GAIN GMA5 GMA4 GMA3 GMA2 GMA1 GMA0 (dB) GRA5 GRA4 GRA3 GRA2 GRA1 GRA0 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6(1) -5 -4 -3 -2 -1 -0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 GAIN GMA5 GMA4 GMA3 GMA2 GMA1 GMA0 (dB) GRA5 GRA4 GRA3 GRA2 GRA1 GRA0 +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15(2) +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 Notes 1. Default value `rec prog-amp' GRAx. 2. Default value `sending prog-amp' GMAx. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
Sidetone balance impedance Internal balance impedance Zoss to match the external line impedance Zline to give optimum sidetone suppression. Zoss = Rsa + (Rsb // Cs). The optimum setting of Rsa depends on the value of the set impedance. To safeguard stable operation of the anti-sidetone circuit under all practical conditions, the following condition must be fulfilled: Rsa 0.5Ra. Table 14 Programming Rsa ZOSA3 ZOSA2 ZOSA1 ZOSA0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. Default value. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Rsa () 134 153 193 221 246 277 295 341 369 443 492(1) - - - - - MSP 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. Default value. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Table 15 Programming Rsb ZOSB MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 1. Default value. Table 16 Programming Cs ZOSP LSP 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PCA1070
Rsb () 465 637 710 803 893 1003 1259(1) 1410 1572 1773 1978 2216 - - - -
Cs (nf) 5 55 58 69 76 85 96 105 121 134(1) 145 166 186 207 232 259
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
Line current control Table 17 Bit code LCx and DC line current LC4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
PCA1070
Iline (typ.) (mA) <12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0 42.5 45.0 47.5 50.0 52.5 55.0 58.0 61.0 64.0 66.5 69.0 71.5 74.0 77.5 80.0 82.5 85.0 88.0 91.0 >94.0
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL VLN Vi VDD Vn Ii Ptot Tstg Tamb HANDLING PARAMETER positive line voltage at pin LN input voltage on pins SLPE, DOC, REG, TX and LSI supply voltage voltage on all other pins input current total power dissipation storage temperature operating ambient temperature MIN. -0.8 -0.8 -0.8 -0.8 -10 - -40 -10
PCA1070
MAX. +12 +12 +7.0 +7.0 +10 250 +125 +60 V V V V
UNIT
mA mW C C
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth j-a DIP24 SO24 PARAMETER thermal resistance from junction to ambient in free air 54 74 K/W K/W VALUE UNIT
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
TEST CONDITIONS AND PARAMETER SETTINGS FOR THE CHARACTERISTICS Table 18 Test conditions SYMBOL Iline VSS f Ip IVP fclk Tamb Zline Rm Rt 150 150 VALUE 20 0 1000 0 0 3.597545 25 220 + 820 // 115 nF UNIT mA V Hz A A MHz C
PCA1070
Table 19 Test settings and control bits. All values, except RFC, are default. Programmable via the I2C-bus; bit codes are given in Chapter "I2C-bus programming". SYMBOL VDCx ZSAx ZSBx ZSPx GMAx GRAx ZOSAx ZOSBx ZOSPx DST DLT RFC HPL PDx RRG RM SM DPI VALUE 100 010 011 0011 001111 100110 1010 0110 1001 0 0 0 0 00 0 0 0 0
1997 Jun 20
18
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
PCA1070
CHARACTERISTICS All parameters are measured in the test circuit of Fig.7 under the conditions specified in Tables 18 and 19; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - 4.7 3.1 5.9 0.4 4.7 3.1 5.9 0.4 20 5.0 4.83 6.5 - - - - - - 7.0 1 1.9 3.4 4.73 145 7.5 - - - 5.2 - - TYP. MAX. UNIT
DC line interface: LN, TX, SLPE and REG Iline VSLPE VSLPE(min) VSLPE(max) VSLPE(step) VSLPE VSLPE(min) VSLPE(max) VSLPE(step) VSLPE VLN line current operating range DC voltage at SLPE minimum selectable value step resolution DC voltage at SLPE minimum selectable value with or without clock; fast start-up; DST = 1 fast start-up; DST = 1; VDCx = 000 17 reduced sending level with or without clock VDCx = 000 12 4.3 2.8 5.4 - - - - - - 4.6 140 17 5.1 3.4 6.4 - - - - - - 5.4 mA mA V V V V V V V V mV V V V V V V V ms
maximum selectable value VDCx = 111
maximum selectable value fast start-up; DST = 1; VDCx = 111 step resolution variation with temperature DC line voltage at LN fast start-up; DST = 1 at Tamb = -10 C to +60 C with respect to 25 C with or without clock Iline = 12 mA Iline = 120 mA
VLN
DC line voltage at LN at low line current
with or without clock; Iline = 0.25 mA Iline = 2 mA Iline = 4 mA Iline = 7 mA
tDC VTX
DC start-up time
CVDD = 470 F; no clock; note 1 external PNP disconnected; VSLPE = 2 V; VREG = 1.5 V; VDD = VVMC = 2.5 V; ITX = 0 mA VSLPE = 3 V; VREG = 2.5 V; VDD = VVMC = 2.5 V; ITX = 1.6 mA
TX: DRIVE OUTPUT FOR EXTERNAL PNP output voltage at TX 1.45 V
- - - - -
2.2 65 65 0.5 1
- - - - -
V ms ms ms ms
tSW
switching time DC voltage at SLPE
VSLPE steps from 3.1 V to 5.9 V; note 2 VSLPE steps from 5.9 V to 3.1 V; note 2 fast start-up; DST = 1; VSLPE steps from 3.1 V to 5.9 V; note 2 fast start-up; DST = 1; VSLPE steps from 5.9 V to 3.1 V; note 2
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SYMBOL PARAMETER CONDITIONS MIN. TYP.
PCA1070
MAX.
UNIT
Supplies: VDD, VMC, VP and SLPE VDD operating supply voltage note 3 relaxed performance; note 4 VDD; SUPPLY PIN IDD internal current consumption VDD = 2.5 V power-down; PDx = 01; SCL = 1; SDA = 1 standby; PDx = 11; SCL = 1; SDA = 1 VDD: PERIPHERAL SUPPLY Ip current available for peripheral circuitry VDD = 2.9 V; RM = 1; SM = 1 VDD = 2.5 V; RM = 1; SM = 1 VVMC = 2.5 V power-down; PDx = 01; VVMC = 2.5 V; SCL = 1; SDA = 1 standby; PDx = 11; VVMC = 2.5 V; SCL = 1; SDA = 1 VP: SUPPLY OUTPUT FOR ELECTRET MICROPHONE VP ZVP PSRVP output voltage output impedance power supply rejection IVP = 500 A f = 300 Hz f = 300 Hz; note 5 1.6 - - 1.9 40 65 - - - V dB - - - - - 4.9 6.5 - - 10 10 5 mA mA A A A - - - 2.3 30 2 - 100 5 mA A A 2.5 1.8 - - 6 2.5 V V
VMC: SENSE INPUT MICROCONTROLLER SUPPLY VOLTAGE IVMC input current 4 4 2
Reset functions: VDD, VMC and RMC INTERNAL RESET VDD(sw) switching level of VDD below which internal reset is active Tamb = -10 to +60 C; note 6 1.0 1.2 1.4 V
RMC: RESET OUTPUT FOR MICROCONTROLLER VVMC(sw) voltage level at pin VMC note 7 where RMC changes state power-down; PDx = 01; note 7 standby; PDx = 11; note 7 VVMC/T voltage variation with ambient temperature Tamb = -10 to +60 C power-down; PDx = 01; Tamb = -10 to +60 C standby; PDx = 11; Tamb = -10 to +60 C 1.8 1.8 1.8 - - - 2.0 2.0 2.1 0 0 +3 2.2 2.2 2.4 - - - V V V mV/C mV/C mV/C
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SYMBOL PARAMETER CONDITIONS MIN. TYP.
PCA1070
MAX.
UNIT
Sending channel: MIC+, MIC-, DTMF, OMIC, LN, SCR, REG and LSI MIC+ AND MIC-: MICROPHONE INPUTS ZMIC CMRRMIC VMIC(peak) GM GM(min) GM(max) GM(step) GM input impedance common mode rejection ratio allowed input signal voltage level (peak value) gain MIC+/MIC- to LN minimum selectable gain maximum selectable gain step resolution gain variation with frequency at f = 300 Hz and 3400 Hz with respect to 1 kHz; note 9 GMAx = 000100 GMAx = 011001 differential single-ended note 8 60 30 - - 39.5 28.5 49.5 - - - - - - 100 50 72 - 41 30 51 1 - 0.2 0 150 - - - 70 42.5 31.5 52.5 - +0.3/-0.7 - 0.5 - - - - 22 2 22 - +0.3/-0.7 - 0.5 k k dB mV dB dB dB dB dB dB dB ms
gain variation with ambient at Tamb = -10 to +60 C with respect to 25 C temperature gain variation with line current tACM GM RDTMF CDTMF GDTMF GDTMF(min) GDTMF(max) GDTMF(step) GDTMF AC start-up time at Iline = 100 mA with respect to 20 mA; note 9 CVDD = 470 F; note 10 SM = 1
Sending mute/privacy switch
reduction of GM parallel input resistance parallel input capacitance gain from DTMF to LN minimum selectable gain maximum selectable gain step resolution gain variation with frequency 100 dB
DTMF: DUAL TONE MULTI-FREQUENCY INPUT SM = 1 SM = 1 SM = 1 SM = 1; GMAx = 100101 SM = 1; GMAx = 001111 SM = 1 SM = 1; at f = 300 Hz and 3400 Hz with respect to 1 kHz; note 9 100 - 20 0 20 - - - - 200 45 21 1 21 1 - 0.2 0 k pF dB dB dB dB dB dB dB
gain variation with ambient SM = 1; at Tamb = -10 to +60 C temperature with respect to 25 C gain variation with line current SM = 1; at Iline = 100 mA with respect to 20 mA; note 9
Confidence tone
GCTS GCTS(min) GCTS(max) GCTS(step) gain from DTMF to QR+/QR-; minimum selectable gain maximum selectable gain step resolution RM = 1; SM = 1; notes 11 and 12 RM = 1; SM = 1; GRAx = 111001 RM = 1; SM = 1; GRAx = 100000 RM = 1; SM = 1 - - - - -25 -40 -19 - - - dB dB dB dB
0.5 to 1 -
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SYMBOL PARAMETER CONDITIONS MIN. - dynamic limiter not active; note 13 - TYP. - -
PCA1070
MAX.
UNIT dB
OMIC: MICROPHONE PREAMPLIFIER OUTPUT ZOMIC GOMIC output impedance gain from MIC+/MIC- to OMIC 400 20
LN: SENDING CHANNEL OUTPUT; notes 14 and 15 BRL balance return loss ZLN with Zref = 220 + (820 // 115 nF) Zline = ; f = 300 Hz Zline = ; f = 1 kHz Zline = ; f = 3.4 kHz 20 20 20 - ZSAx = 001; note 17 ZSAx = 11x - - - - ZSBx = 001; notes 17 and 18 ZSBx = 1x1 - - - - 37 35 25 - - - - - - - - - - - - dB dB dB Hz
Selectable values for Zset = Ra + (Rb // C) with C = 1/(2 x Rb x fp); note 16
Ra Ra(min) Ra(max) Ra(step) Rb Rb(min) Rb(max) Rb(step) fp non-shunted resistance of Zset minimum selectable value for Ra maximum selectable value for Ra step resolution for Ra shunted resistance of Zset minimum selectable value for Rb maximum selectable value for Rb step resolution for Rb pole frequency determining shunt capacitance C minimum selectable fp maximum selectable fp multiplication factor for fp noise output voltage ZSPx = 0000 ZSPx = 0111; note 19 fp(x + 1) = n x [fp(x)] psophometrically weighted (O41 curve) 200 0 600 100 800 600 1000 100 1915
fp(min) fp(max) n vLN(noise)
- - - -
828 5859 1.322 -76
- - - -
Hz Hz dBmp
Dynamic limiter
VLN(p-p) threshold of dynamic limiter (peak-to-peak) 3.1 DLT = 1 low voltage condition; VSLPE = 3.1 V low current condition; Iline = 9 mA THD total harmonic distortion Vi = 12 mV (RMS) + 10 dB Vi steps from 12 to 38 mV (RMS) Vi steps from 38 to 12 mV (RMS) 2.2 - - - - - 3.5 2.6 2.4 2.6 2.5 3.9 3.0 - - 5.0 - - V V V V %
Dynamic behaviour of limiter; note 20
tatt trel attack time release time 1.5 90 ms ms
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SYMBOL PARAMETER CONDITIONS MIN. - reduced sending gain; GM = 30 dB; GMAx = 000100 Iline = 12 mA Iline = 7 mA Receiving channel: LN, LSI, OREC, QR+ and QR- QR+, QR-: RECEIVING AMPLIFIER OUTPUTS ZQR+, ZQRGRS GRS(min) GRS(max) GRS(step) GRS GRS GRS tACR vQR(p-p) output impedance gain from LN to QR+/QRminimum selectable gain maximum selectable gain gain step resolution gain variation with frequency gain variation with temperature gain variation with line current AC start-up time maximum output voltage swing (peak-to-peak) at f = 300 Hz and 3400 Hz with respect to 1 kHz; note 9 at Tamb = -10 to +60 C with respect to 25 C at Iline = 100 mA with respect to 20 mA; note 9 CVDD = 470 F; note 10 VDD = 5 V; GRAx = 001011; Rt = ; RFC = 1; VLN = 2 V (RMS) HPL = 1; VDD = 5 V; GRAx = 001011; Rt = ; RFC = 1; VLN = 2 V (RMS) vQR(rms) output voltage (RMS value); THD = 2% HPL = 1; GRAx = 000011; note 22 HPL = 1; Rt = 450 ; GRAx = 000011; note 22 RFC = 1; Ct = 80 nF; f = 3.4 kHz; GRAx = 000011; note 22 single-ended; HPL = 1; Zt = 150 + 100 F at QR-; GRAx = 001001; note 22 vQR(noise) VQR(offset) noise output voltage DC offset voltage between QR+/QR- psophometrically weighted (O41 curve) single-ended note 21 GRAx = 110011 GRAx = 001011 - -7.5 -20.5 9.5 - - - - - - 4 -6 -19 11.0 1 - 0.2 0 140 2.3 - - - - TYP. - - - -
PCA1070
MAX.
UNIT
SCR: PIN FOR SENDING CURRENT RESISTOR VSCR voltage at pin SCR 0.28 0.26 0.22 0.13 V V V V
dB dB dB dB dB dB dB ms V
-4.5 -17.5 12.5 - 0.5 - 0.5 - -
-
5.9
-
V
0.45 0.84 0.9 0.45
- - - -
- - - -
V V V V
- -
-82 -
- 100
dBmp mV
OREC: OUTPUT RECEIVE PREAMPLIFIER ZOREC GOREC output impedance gain from LN to OREC note 13 - - 1000 -6 - - dB
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SYMBOL PARAMETER CONDITIONS MIN. - ZOSAx = 0000 ZOSAx = 1010; note 24 - - - ZOSBx = 0000 ZOSBx = 1011; note 24 - - - ZOSPx = 0001; note 25 ZOSPx = 1111; note 24 - - TYP. - - - - - - - - -
PCA1070
MAX.
UNIT nF nF nF
Selectable values for Zoss = Rsa (Rsb // Cs); note 23
Rsa Rsa(min) Rsa(max) Rsb Rsb(min) Rsb(max) Cs Cs(min) Cs(max) non-shunted resistance of Zoss minimum selectable value Rsa maximum selectable value for Rsa shunted resistance of Zoss minimum selectable value for Rsb maximum selectable value for Rsb shunt capacitance of Zoss minimum selectable value for Cs maximum selectable value for Cs gain from MIC+/MIC- to QR+/QR- 492 134 492 1259 465 2216 134 55 259
Sidetone suppression; note 26
GSTS Zline = 492 + (1259 // 134 nF); f = 300 Hz Zline = 492 + (1259 // 134 nF); f = 1 kHz Zline = 492 + (1259 // 134 nF); f = 3.4 kHz Dial output connection: DOC (open-drain output) IDOC output sink current VDOC = 12 V - 0 400 100 - - nA A DPI = 1; VDOC = 0.4 V; VDD = 2.5 V 200 Line current control: LN and SLPE Iline(min) minimum value of DC line LCx = 00001 current that can be read as a bit code via the I2C-bus maximum value of DC line LCx = 11110 current that can be read as a bit code via the I2C-bus DC line current step resolution note 27 - 15 mA - - - 11 5 9 15 10 15 dB dB dB
Iline(max)
-
91
-
mA
Iline(step)
-
2.5
-
mA
I2C-bus inputs/outputs: SDA and SCL in accordance with standard note 28 - - -
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SYMBOL Clock input: CLK vCLK(p-p) fCLK/fCLK RCLK CCLK Notes 1. Time needed to reach at start-up the default DC voltage VSLPE (10% from its final value): input signal voltage level (peak-to-peak value) frequency tolerance input series resistance input series capacitance note 29 200 - - - - - 800 4 PARAMETER CONDITIONS MIN. TYP.
PCA1070
MAX.
UNIT
VVMC - VSS mV 0.5 - - % k pF
a) Time depends strongly on the value of the capacitor(s) at VDD and VMC; with a lower value of CVDD the DC start-up time decreases. b) The start-up time can be reduced considerably by programming the bit code DST = 1 during the start-up procedure. In practice this is possible as soon as the microcontroller has become operational. 2. Time needed to reach the DC voltage VSLPE within 10% from its final value) after reprogramming VDCx. 3. The supply voltage VDD is determined by the regulated DC voltage at pin SLPE and by the voltage drop between pin SLPE and VDD; see Chapter "Functional description". 4. Relaxed performance means: parameters can deviate from their specified values. 5. Rejection between supply pin VDD and VP. Rejection between pin LN and VP can be calculated by adding the attenuation of the first-order low-pass filter (R = 250 , C = 150 F) between SLPE and VDD. 6. If VDD is above this level, the default values have been loaded into the internal registers. 7. RMC changes from logic 1 to logic 0 when voltage on pin VMC is increasing; RMC changes from logic 0 to logic 1 when voltage on pin VMC is decreasing; see Fig.4. 8. Common mode signal is applied via 2 x 470 external resistors connected to pins MIC+ and MIC-. 9. Not tested, guaranteed by design. 10. Time needed to reach default settings (3 dB). 11. At low gain settings the confidence tone gain will be slightly higher than the specified value due to a residual signal. 12. GCTA, the confidence tone gain for asymmetrical drive, equals GCTS -6 (in dB). 13. To be left open-circuit in application. 14. The AC set impedance between pin LN and VSS consists of Ra + (Rb // C) in parallel with an artificial inductor Leq and internal resistors Rp and RLSI and internal capacitor Cp. See Chapter "Functional description". 15. Balance Return Loss indicates the deviation of an impedance with respect to a reference impedance. BRL = 20 log (ZLN + Zref)/(ZLN - Zref) where ZLN Ra + (Rb // C) is the impedance seen into pin LN Zref = Ra(ref) + (Rb(ref) // Cref) is the reference impedance. 16. Without clock the set impedance is automatically set to Zset = 600 (typical). 17. The combination Ra = 0 and Rb = 0 is not allowed (see Tables 9 and 10, note 1). 18. Value logic 0 can also be programmed. 19. Value fp = 12 kHz can also be programmed. 20. Attack and release times are also valid under low current and voltage conditions. 21. GRA, the receiving channel gain for asymmetrical drive equals GRS -6 (in dB). 22. The maximum possible output swing depends on the DC conditions (the programmed voltage VSLPE and the load on the supply pin VDD) and on the gain setting of the receiving channel.
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
PCA1070
23. The internal balance impedance Zoss to match the external load impedance at pin LN (Zline = Zoss) for optimum sidetone suppression; Zoss = Rsa + (Rsb // Cs); without clock the sidetone balance impedance is automatically set to Zoss = 600 (typical). 24. Other values can be found in Tables 14, 15 and 16. 25. Value Cs = 5 nF can also be programmed. 26. Gain sending channel GM = default (typical 41 dB); gain receiving channel Grec = default (typical -6 dB); sidetone gain GSTS minimum sidetone suppression at f = 300 Hz and 3400 Hz is: GM + GR - Gst(max) = 41 - 6 - 15 = 20 dB. GSTA, the sidetone gain for asymmetrical drive equals GSTS -6 (in dB). 27. Indication only; exact values can be found in Table 16. 28. Standard I2C-bus specifications are valid for VDD 2.5 V. Relaxed specifications for VDD = 1.8 to 2.5 V. 29. Recommended accuracy of input frequency; a higher tolerance will cause parameters to deviate from their specified values; note that all parameters are specified with the reference input clock frequency fclk = 3.579545 MHz.
1997 Jun 20
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Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
TEST AND APPLICATION INFORMATION
PCA1070
The test circuit is illustrated in Fig.7. The basic application circuit is illustrated in Fig.8. An interrupter with an N-channel depletion MOS transistor (e.g. BSD254A or BSP124) is shown. It is intended for applications where a low DC line voltage is required. An interrupter with an N-channel enhancement MOS transistor (e.g. BSN304A or BSP130) can be used for applications where a relatively high DC line voltage is allowed. An application circuit for applications where a low DC line voltage and long line interrupts are required, is illustrated in Fig.9 (interrupter with an N-channel depletion MOS transistor).
handbook, full pagewidth
VDOC
100 F Zline S1 Iline 12 to 140 mA 1 2 Vrec
+ VLN -
3.3 nF
100 nF
20
470 nF 5V 250 150 F Ip I2C-BUS MASTER TRANSCEIVER
IDOC DOC ITX TX LSI LN SLPE REG VDD
VMC SDA SCL CLK
PCA1070
SCR 100 Vref OMIC OREQ VP MIC+ MIC- QR+ VMIC IVP + Rm Vm + - Rt Vt -
DTMF RMC TST QR- VSS + VDTMF - + Vclk -
100 nF
MGE345
Definitions: Gain sending channel GM = 20 log (VLN/VMIC) with S1 in position 1; VDTMF = 0. Gain DTMF amplifier GDTMF = 20 log (VLN/VDTMF) with S1 in position 1; Vm = 0. Gain receiving channel Grec = 20 log (VT/VLN) with S1 in position 2; Vm = 0. Sidetone gain Gst = 20 log (VT/VMIC) with S1 in position 1; VDTMF = 0.
Fig.7 Test circuit of the PCA1070.
1997 Jun 20
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dbook, full pagewidth
1997 Jun 20
RINGER OUTPUT STAGE HS2 I2C-bus 1 M 20 250 150 F
Philips Semiconductors
a/b
HS1
Multistandard programmable analog CMOS transmission IC
b/a
28
DOC LSI LN SLPE REG VDD SCL CLK VMC SDA TX SDA SCL
PXE
VDD T1
PCA1070
DTMF RMC TST Vref OMIC OREQ VP MIC+ MIC- QR+ QR- VSS SCR
TONE
MICROCONTROLLER DTMF CE/T0 EEPROM RESET
100
VSS XTAL1 XTAL2 ROM COL
100 nF
KEYBOARD
MGE344
ELECTRET
Product specification
PCA1070
Fig.8 Basic application diagram.
dbook, full pagewidth
1997 Jun 20
RINGER OUTPUT STAGE HS2 I2C-bus 1 M 20 250 470 F 47 F
Philips Semiconductors
a/b
HS1
Multistandard programmable analog CMOS transmission IC
b/a
29
DOC LSI LN SLPE REG VDD SCL CLK VMC SDA TX SDA SCL
PXE
VDD T1
PCA1070
DTMF RMC TST Vref OMIC OREQ VP MIC+ MIC- QR+ QR- VSS SCR
TONE
MICROCONTROLLER DTMF CE/T0 EEPROM RESET
100
VSS XTAL1 XTAL2 ROM COL
100 nF
KEYBOARD
MGE343
ELECTRET
Product specification
PCA1070
Fig.9 Application diagram.
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
PACKAGE OUTLINES DIP24: plastic dual in-line package; 24 leads (600 mil)
PCA1070
SOT101-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 24 13 MH wM (e 1)
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.20 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 32.0 31.4 1.26 1.24 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.10 e1 15.24 0.60 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT101-1 REFERENCES IEC 051G02 JEDEC MO-015AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-23
1997 Jun 20
30
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
PCA1070
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1997 Jun 20
31
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
PCA1070
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used * The longitudinal axis of the package footprint must be parallel to the solder flow * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Jun 20
32
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCA1070
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 20
33
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
NOTES
PCA1070
1997 Jun 20
34
Philips Semiconductors
Product specification
Multistandard programmable analog CMOS transmission IC
NOTES
PCA1070
1997 Jun 20
35
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417027/00/03/pp36
Date of release: 1997 Jun 20
Document order number:
9397 750 00949

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